As technology progresses, integrated circuits are becoming larger and more complex. They are also becoming more expensive to develop. As a result, the cost of a design error is also increasing, which puts more emphasis on checking the designs before they are fabricated in order to reduce the risk of a design error.
Using timing as an example, it is becoming increasingly important to confirm that an integrated circuit does not violate timing constraints before it is released to manufacturing. However, the increasing size and complexity of integrated circuits, coupled with the increasing stringency of timing requirements, means that it has become necessary to use sophisticated tools to assist in this task. Furthermore, these tools must be optimized for performance and accuracy. Even with current technology, automated timing analysis can take a long time. In addition, overly optimistic results will miss possible design errors and overly pessimistic results will impose unnecessary constraints on the chip design.
One subtask for timing analysis is to estimate a circuit's behavior under specific operating conditions (e.g., at a specific temperature, subject to a specific voltage variation and/or assuming a specific process variation). Since integrated circuit designs are evaluated at many different operating conditions and since a chip contains a very large number of circuits, this subtask is repeated many many times during the course of designing an integrated circuit.
One approach to this subtask is to provide a set of cell libraries, each of which characterizes certain basic circuits (i.e., cells) at a specific operating condition. The library operating conditions often will not match the operating condition of design cell instances because of variations such as environmental, operational, or process variations, so the data in the libraries must be scaled to estimate the circuit's behavior at the operating condition of interest. This is typically done by using a derating factor. The derating factor is a multiplier that is supposed to account for differences between the library operating conditions and the actual operating conditions. For example, if the library is characterized at 1.8V, but the actual voltage for a timing analysis scenario is 1.6V, then a derating factor can be used to adjust the behavior predicted by the library.
However, derating factors are fairly simplistic. They are a fudge factor of sorts which can be sufficient for older process technologies but may not be sufficient as technology progresses, for example in the case of deep submicron processes. For more complex analysis, derating factors typically do not provide sufficiently accurate results. They also have difficulty handling scaling across many operating conditions simultaneously.
Accordingly, there is a need for improved approaches to scaling circuit behavior to different operating conditions.